Binary counter



W. R. SMITH BINARY COUNTER Oct. 11, 1966 2 Sheets-Sheet 1 Filed Feb. 18, 1963 R.H m l V M ms N W o wzfiz T 7 292N153 B o N F N 1A -it HIS ATTORNEY W. R. SMITH BINARY COUNTER Oct. 11, 1966 2 Sheets-Sheet 2 Filed Feb. 18, 1963 BIN ARY OUTPUT RELAYS R2 R3 R4 2 CORES C2 C3 C4 R! DECIMAL NUMBER Cl C CLEAR 8 =SET U =PlCKED-UP D=DROPPED OUT INVENTOR.

H W M W HIS ATTORNEY United States Patent York Filed Feb. 18, 1963, Sci. No. 258,999 14 Claims. (Cl. 340174) This invention relates to counting circuits, and more particularly to binary counter circuits utilizing relays in combination with apertured magnetic cores.

Binary counting circuits have been constructed utilizing switching devices comprising either relays exclusively, or apertured magnetic cores exclusively. Heretofore however, it has not been considered feasible to combine both types of circuit elements in a single counter circuit. Yet, use of but one type of circuit element exclusively carries with it certain disadvantages. For example, counters utilizing solid state circuit elements as switching devices, whether they be either active or passive elements, generally require complex wiring in order to 'be rendered operative. Moreover, such counters are generally incapable of producing large output currents without requiring additional amplification. On the other hand, counters utilizing relays as switching devices although readily lending themselves to simple circuit wiring, generally require heavy input currents. These heavy input currents may not present problems when counting of relatively few bits of information is required. However, when a large number of bits must be counted, many relays may be energized or deenergized simultaneously, producing large, potentially harmful power supply current surges. Furthermore, since relays are slower acting devices than solid state circuit elements, relay actuation time, which is cumulative, may necessitate very slow operating speeds in counters handling many bits of information. Ideally therefore, a binary counter should incorporate the best features of both solid state circuit element counters and relay counters. Such combination of desirable features has been achieved in the instant invention by creation of a counter utilizing an optimum combination of relays and apertured magnetic cores wherein both the relays and cores perform switching and storage operations.

The invention generally contemplates a binary counter for registering a plurality of bits of information, utilizing a separate relay and a separate multi-aperture magnetic core for registering each separate bit of information. Counter input pulses comprising bits of information are provided from a pair of switch contacts which may be operated either manually or by actuation of an input relay. Each time the switch contacts are closed or the relay is actuated by an input pulse of energy, a multiaperture core is set by discharge of a charged capacitor.

Starting with a count of zero registered in the counter, the first input pulse sets a first core. The set core then energizes the relay associated therewith, which thereby provides a readout indicative of presence of the single bit of information represented by the first input pulse. Upon receipt of the next following input pulse, the set core is cleared by the capacitor discharge. Current produced by the discharge sets a second multi-apertured core, thereby energizing the relay associated with the second core. The next following pulse then sets the first core, causing it to energize the relay associated therewith, while the relay associated with the second multi-aperture core remains energized. The next following input pulse causes both the first and second cores to be cleared and a third core to be set by the capacitor discharge. This causes the relays associated with the first two cores to deenergize and the relay associated with the third core 3,278,918 Patented Oct. 11, 1966 to energize. The counting circuit may be extended to as many cores and relays as required to handle any number of desired bits of information, merely by increasing the number of stages in the counter.

One object of this invention is to provide a binary counter utilizing a single relay and a single multi-aperture core bit of information handled .by the counter.

Another object of this invention is to provide a fastacting binary counter for producing heavy output currents.

Another object of this invention is to provide a rugged, compact binary counter utilizing a minimum number of circuit elements.

Another object is to provide a binary counter utilizing more than one type of switching device.

Another object is to provide a binary counter circuit which can be expanded to handle a large number of bits of information without materially increasing power supply requirements.

These and other objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic diagram of the binary couner utilizing a single relay and single multi-aperture core per bit of information counted.

FIG. 2 is a chart showing the states of current on the output conductors for various numbers registered in the counter.

Turning now to FIG. 1 for a detailed description of the novel binary counter, there is shown a group of apertured magnetic cores C1-C4, each core having a major aperture, an input minor aperture and an output minor aperture. Each core has associated therewith a relay Rl-R4 respectively. Relays R1, R2, R3 and R4 are coupled to output minor apertures 2, 4, 6 and 8 of cores C1, C2, C3 and C4, respectively, through series-connected capacitors 21, 23, 25 and 17, respectively. Each relay R1, R2, R3 and R4 has connected in parallel therewith a diode 20, 22, 24 and 26, respectively.

Remanent magnetic state of each core is altered by front and back contacts 11, 13, 15 and 17 of relays R1, R2, R3 and R4, respectively. Thus, each core is set by passage of energy through input minor apertures 1, 3, 5 and 7 of cores C1, C2, C3 and C4 from respective back contacts 11, 13, 15 and 17 of relays R1, R2, R3 and R4, respectively, while the cores are cleared by passage of energy through their major apertures from front contacts 11, 13, 15 and 17, respectively. Output signals are provided on conductors coupled to front contacts 12, 14, 16 and 18 of relays R1, R2, R3 and R4, respectively. Energization of front contact 12 indicates registration of at 2 digit, energization of front contact 14 indicates registration of a 2 digit, energization of front contact 16 indicates registration of a 2 digit, and energization of front contact 18 indicates registration of a 2 digit. The front contacts may be connected to suitable utilization means, such as computing or indicating means (not shown).

The counter receives input pulses through a pair of input terminals coupled to an input relay R5. A capacitor 9 charges to a voltage amplitude equal to DO. supply voltage amplitude through back contact 19 of relay R5. Upon energization of relay R5, capacitor 9 discharges through front contact 19 and through predetermined apertures of cores'Cl, C2, C3 and 04, depending upon the number registered in the counter, changing the rema nent magnetic states of one or more of these cores and thereby producing an output indicative of the number registered in the counter. Obviously, contact 19 may be operated manually or by mechanical input means other than a relay.

. cores C1-C4 are in the clear condition.

A radio frequency signal is coupled from an RF. signal generator through output minor apertures 2, 4, 6 and 8 of cores 01, C2, C3 and C4, respectively, in order to produce sufiicient power output from any set core for energization of the relay associated therewith. The radio frequency signal serves to alternately prime and drive the output minor aperture of each se-t c-ore at a radio frequency rate, thereby providing nondestructive core readout.

In operation, assume the counter has the decimal number zero stored therein. Under these circumstances, Capacitor 9 acquires a charge through back contact 19 of relay R5, during the time in which relay R5 is deenergized. When a pulse is applied across the input terminals to relay R5, front contact 19 of the relay closes. This causes discharge of capacitor 9 through front contact 19 of relay R5, back contact 11 of relay 'R-1 and input minor aperture 1 of core 01, thereby setting the core.

When core 01 is set, radio frequency output current is induced at minor aperture 2 which charges capacitor 21 when the radio frequency output voltage is poled in the forward direction across diode 20, and which provides energization across relay R1 when the voltage applied across diode 20 is poled in the reverse direction. When the voltage across diode 20 is reverse-polarized, voltage across relay R 1 is equal to the sum of the voltage produced at minor aperture 2 plus the voltage across capacitor '21, thereby effectively increasing the voltage applied across the relay. Relay R1 remains energized as long as core C1 is set, thereby maintaining front contact 12 closed. This produces a voltage at the output terminal indicative of presence of a 2 stored in the binary counter. a

When the input pulse to the counter is removed, relay R5 deenergizes, closing back contact 19 and again permitting capacitor 9 to acquire a charge. When the next pulse to be counted is applied to relay R5, front contact 19 again closes and capacitor 9 discharges through front contact 11 of relay R-1 and through the major aperture of core 01, clearing the core, and through back contact 13 of relay -R2, setting core C2 through minor aperture 3. Relay R2 then energizes with radio frequency energy applied through series-connected capacitor 23 and parallel-connected diode 22. Capacitor 23 serves the same function for relay R2 as does capacitor 21 for relay R1, while diode 22 serves the same function for relay R2 as diode 20 does for relay R1. At this point, front contact 14 of relay R2 is closed, applying energy to the output terminal indicative of presence of a 2 indicating that a decimal count of two is now stored in the counter.

Again, when the input pulse counted is removed from relay R5, back contact 19 of relay R5 closes, again permitting capacitor 9 to acquire a charge. When the next pulse is applied to the counter, capacitor 9 discharges through front contact 19 of relay R5 and back contact 11 of relay R1, setting core 01 through its minor aperture 1. This causes relay R1 to energize, thereby applying a voltage to the output terminal indicative of presence of a 2. At this point, the output terminals indicative of 2 and 2 are both energized, indicating that the counter has counted three input pulses.

When the next pulse is applied to relay R5, capacitor 9 discharges through front contact 19 of relay R5 and front contact .11 of relay R1, clearing core C1 through its major aperture, through front contact 13 of relay R2, clearing core C 2 through its major aperture, and through back contact 15 of relay R3, setting core C3 through its minor aperture 5. This causes energization of relay R3 with radio frequency energy received from output minor aperture 6 of core 03' through a seriesconnected capacitor 25 to the relay, across diode 24. Again, capacitor 25 and diode 24 perform the same function as capacitor 21 and diode 20, respectively. At this point, relay R3 is energized and its front contact 16 is closed, while relays R11 and R2 are deenergized. This causes energization of the output terminal indicative of presence of a 2 indicating a decimal count of four is stored in the binary counter.

Core C4 provides indication of a 2 when its input minor aperture 7 receives an input signal through back contact 17 of relay R4, and its output minor aperture 8 thereby provides radio frequency enegization for relay R4 through series-connected capacitor 27 and across parallel-connected diode 26, which serve the same functions as capacitor 21 and diode 20, respectively.

Because four multi-aperture cores are involved and four relays associated therewith are also involved, the counter is capable of counting from zero to fifteen pulses, inclusive. When the sixteenth pulse is counted, all four cores will clear, and the output number registered will be zero. The next input pulse to relay R5 will start the counting cycle over again, beginning from zero.

For increasing the counting capabilities of the counter, it is merely necessary to add additional stages similar to the four shown in FIG. 1. Thus, to indicate registration of the digit 2 providing the counter with capabilities of counting from zero to thirty-one inclusive, it is merely necessary to add a fifth multi-aperture magnetic core and a fifth relay similar to relay R4, coupled through a diode and capacitor in a fashion similar .to that of core C4 and relay R4. Moreover, still further additional s-tages may be added if desired.

FIG. 2 is a chart showing conditions of cores C1-C4 and relays R1-R4 in the circuit of FIG. 1 for an applied decimal number of pulses from zero to fifteen, inclusive. Thus, as indicated in the chart, when the number of pulses counted is zero, cores C1-C4 are clear and relays R1-R4 are dropped out, so that the output signals on terminals 2-2 are zero. When the decimal number of pulses counted is one, core C1 is set while cores C2-C4 are clear. This means that relay R1 is picked-up and relays R2-R4 are dropped-out. The output terminals then register a voltage, indicated by a one on the 2 terminal, and no voltage, indicated by zeros, on the 2 2 and 2 terminals. Thus, the conditions for the circuit of FIG. 1 for any decimal number of pulses from zero to fifteen may be determined from the chart of FIG. 2.

Thus, there has been shown a binary counter which through cooperation of magnetic cores and relays utilizes the best features of cores and relays for achieving a simple, rugged and reliable counter requiring a minimum number of components. The circuit provides heavy output currents without amplification, and yet does not require breaking of heavy current as in exclusively relay counting circuits, since each relay is energized individually from its associated core.

Although but one specific embodiment of the present invention has been described, it is to be specifically understood that this form is selected to facilitate in disclosure of the invention rather than to limit the number of forms which it may assume; various modifications and adaptations may be applied to the specific form shown to meet requirements of practice, without in any manner departing from the spirit or scope of the invention.

What is claimed is:

1. A counter for providing binary registration of a counted decimal number comprising a plurality of apertured magnetic cores, a plurality of relays, each said relay being actuated by output from a separate core, means setting each separate core through a back contact of the relay actuated from said core, and means clearing said core through a front contact of the relay actuated from said core and simultaneously changing remanent magnetic state of a subsequent core.

2. A counter for providing binary registration of a counted decimal number comprising a plurality of apertured magnetic cores, a plurality of switching devices, each of said devices being actuated by output from a separate core, means setting each separate core through an output circuit of said device when said device is unactuated, and means clearing said core through a second output circuit of said device when said device is actuated and simultaneously altering remanent magnetic state of a subsequent core.

3. A counter for providing steady binary indication of a counted decimal number comprising an apertured magnetic core, a relay actuated by output from said core, means setting said core through a back contact of the relay, and means clearing said core through a front contact of the relay.

4. A counter for providing binary indication of a counted decimal number comprising a plurality of apertured magnetic cores, a plurality of relays, each of said relays actuated by output from a separate core, means setting each separate core through a back contact of the relay actuated from said core, and means clearing said core through a front contact of the relay actuated from said core and simultaneously altering remanent magnetic state of a subsequent core.

5. The counter of claim 4 including radio frequency signal generating means, and means coupling a radio frequency signal from said generating means to the output of each of said cores whereby each set core provides a radio frequency induced signal for energization of the relay coupled thereto.

6. Means for counting the number of pulses in a pulse train comprising a plurality of apertured magnetic cores, a plurality of relays, each of said relays being actuated by output from a separate core, means setting each separate core through a back contact of the relay actuated from said core, means clearing said core through a front contact of the relay actuated from said core and simultaneously altering remanent magnetic state of a subsequent core, an input relay, means applying the pulse train to the input relay for operation thereof, and means controlled by the input relay for coupling current through the first core of said plurality of cores.

7. The counter of claim 6 including a radio frequency signal generator coupled to each core for inducing energization current in the output of each core to operate the relay actuated said output.

8. A binary counter comprising a plurality of counting stages, each stage comprising an apertured magnetic core, a relay actuated by output from said core, means setting said core through a back contact of the relay, and means clearing said core through a front contact of the relay and simultaneously changing remanent magnetic state of a core in a subsequent counting stage.

9. In a binary counter for providing binary registration of a decimal number, a plurality of storage means of first and second types, each said second type storage means receiving an output signal from a separate one of said first type storage means, means coupling information to a first of said first type storage means for storage therein, means coupling output from the first of said first type storage means to a first of said second type storage means, and means transferring information from the first of said first and second type storage means to subsequent storage means of the first and second type.

10. A counter for providing binary registration of a counted decimal number comprising a plurality of apertured magnetic cores, a plurality of relays, each said relay being actuated by output from a separate core, means switching each separate core to a first remanent magnetic state through a first contact of the relay, and means switching the core to a second remanent magnetic state through a second contact of the relay while simultaneously changing remanent magnetic state of a subsequent core through said second contact.

11. A counter for providing binary registration of a counted decimal number comprising a plurality of apertured magnetic cores, a plurality of switching devices, each of said devices being actuated by output from a separate core, means inducing a first remanent magnetic state in each separate core through an output circuit of said device when said device is unactuated, and means inducing a second remanent magnetic state in said core through a second output circuit of said device when said device is actuated and simultaneously inducing the second remanent state in a subsequent core through said second circuit.

12. A counter for providing steady binary indication of a counted decimal number comprising an apertured magnetic core, a relay actuated by output from said core, means inducing a first remanent magnetic state in said core through a first contact of the relay, and means inducing a second remanent magnetic state in said core through a second contact of the relay.

13. A counter for providing binary registration of a counted decimal number comprising a plurality of multiaperture magnetic cores, a plurality of relays, each said relay being actuated by output from a separate core, means providing set current for each separate core through a back contact of the relay actuated from said core and an input minor aperture of said core, and means providing clear current through said core from a front contact of the relay actuated from said core and simultaneously altering remanent magnetic state of a sub-' sequent core through said front contact.

14. The counter of claim 13 including radio frequency generating means and means coupling a radio frequency signal from said generating means through an output minor aperture of each of said cores whereby each set core provides a radio frequency induced signal for energization of the relay coupled thereto.

References Cited by the Examiner UNITED STATES PATENTS 2,114,016 3/1938 Diamond 235-92 2,772,370 11/1956 Bruce et a1. 23592 3,121,799 2/1964 Mintzer 23592 OTHER REFERENCES Johnston: Multiaperture-Core Counters Give Nondestructive Storage Readout, Electronics, June 16, 1961, pp. 62-64.

MAYNARD R. WILBUR, Primary Examiner. J. F. MILLER, Assistant Examiner. 

3. A COUNTER FOR PROVIDING STEADY BINARY INDICATION OF A COUNTED DECIMAL NUMBER COMPRISING AN APERTURED MAGNETIC CORE, RELAY ACTUATED BY OUTPUT FROM SAID CORE, MEANS SETTING SAID CORE THROUGH A BACK CONTACT OF THE RELAY, AND MEANS CLEARING SAID CORE THROUGH A FRONT CONTACT OF THE RELAY. 